When data is transmitted from one assembly to another assembly, the phase angle of the transmitted data signal is unknown unless the clock is also transmitted. A clock recovery circuit is thus used in the input of the receiver assembly. If only data is transmitted and must then be processed further at the receiver end, it is necessary to find a code inherent in the data. This is done by using a clock recovery circuit to obtain this time clock for the transmitted data from the data.
If the transmitting and receiving assemblies are controlled by a central clock in a larger unit, then, for further processing of the data, the data must once again be matched to the central clock. The phase angle of the data in the receiver must therefore also be determined with respect to the central clock.
This can be done using a traditional phase locked loop (PLL) circuit. In this case, the phases of the data signal and the recovered clock are compared, and the phase angle of the transmitted data signal with respect to the system clock is determined in a feedback arrangement using an analogue phase filter and a voltage controlled oscillator (VCO). One problem that arises in the process when using digital systems is that a conventional phase locked loop contains analogue components, which cannot be directly connected to the digital units in a complete digital system.
However, a system clock is frequently also passed from a central time unit in the system to various data processing units. Each of the data processing units contains its own phase locked synchronization (PLL), in order to obtain a clock signal for that unit from the system clock. In a case such as this, all the clocks in the units are synchronized to the system clock. All these data processing units can thus interchange synchronous data with one another, with the data being received by different units. Data is accordingly transmitted between different synchronous clock areas. The receiving unit must match the phase of the received data to its clock in order to be able to further process the data. If the asymmetry of the time clock in the data processing unit, the time delay in the data transmission process and the typical set-up and hold times in the receiving unit are less than one clock period, then the data can also be transmitted without the associated time clock. The receiving unit can match the data to the applicable clock at any time without any disturbance to the set-up and hold conditions.
However, if these conditions cannot be satisfied in a data transmission system, that is to say the data transfer is not completed within one clock period, the data must be transmitted with the associated time clock. An elastic memory is generally used for such transmission, in order to guarantee correct time matching to the local receiving clock.
However, a clock recovery circuit is frequently used in the receiving unit, in order to avoid transmission of the time clock signal associated with the data signal.
One object of the present invention is to carry out the clock recovery process purely digitally, and at the same time to ensure that the recovery process is essentially insensitive to dynamic phase changes in the data signal.